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6CCE3HAD
6
Spring
15
This module will introduce the design, simulation and synthesis of digital systems (FPGA) using the VHDL and will elaborate on: VHDL design flow; structural, behavioural and dataflow descriptions; VHDL data types and operators; processes and behavioural commands; simulation cycle and delta delays; timing, delays and clocks; sequential circuits; finite state machines; test benches; text input/output; synthesis and realisation; programmable logic devices.
Written examination & coursework
To introduce the design, simulation and synthesis of digital systems using the IEEE VHDL standard and build familiarity and confidence in using associated tools.
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Please note that modules with a practical component will be capped due to educational requirements, which may mean that we cannot guarantee a place to all students who elect to study this module.
Please note that the module descriptions above are related to the current academic year and are subject to change.